1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices such as ROM (Read Only Memory) and EPROM(Erasable and Programmable Read Only Memory) can store data in a memory cell transistor in a binary or multi-value form. In these semiconductor memory devices, a plurality of memory cell transistors are arranged in a matrix. That is, the plurality of memory cells are connected with word lines in a row direction and is connected with digit lines in a column direction. When a storage data is to be read out from a memory cell, bias voltages are applied to the word line and the digit line which are determined in accordance with an address signal. In this way, a quantity of current flowing through the memory cell is sensed and the storage data is read out.
In a conventional semiconductor memory device, each of memory cell transistors is segmented by an element separation area. The source of the memory cell transistor is grounded, the gate thereof is connected with a word line and the drain thereof is connected with a digit line. In such a structure, the structure of the reading circuit can be simplified. However, because a contact with the drain of the memory cell transistor must be formed for every memory cell, the structure is unsuitable for the reduction of a chip area.
To solve such a problem, the arrangement of memory cells of a virtual ground system is proposed. In the semiconductor memory device of this system in which the plurality of memory cell transistors are arranged in a matrix, the source of drain of a memory cell transistor are connected with digit lines in common. Moreover, the source or drain of the memory cell transistor is connected with the source or drain of a neighbor memory cell transistor. For these reasons, the number of drain contacts or source contacts can be reduced and the chip area can be greatly reduced.
When a storage data is read out from a memory cell in the virtual ground system, bias voltages are applied to a selected word line and a selected digit line which are determined in accordance with an address signal, as in the case mentioned above. A quantity of current flowing through the memory cell at this time is sensed by a sense amplifier and the storage data is read. However, the selected digit line to which the memory cell is connected is also connected with a neighbor memory cell which is connected with the same selected word line as the memory cell. Therefore, the bias voltage which has been supplied to a selected digit line diffusion wiring line is supplied to not only the memory cell as the reading operation object but also the neighbor memory cell. Therefore, a read current also flows through the neighbor memory cell through a non-selected digit line diffusion wiring line. As the result, the semiconductor memory device outputs a wrong data. In this way, it is necessary that the non-selected digit line diffusion wiring line is precharged to a level equal to the selected digit line diffusion wiring line. In this case, the read current flows only through the selected memory cell which is connected with the selected digit line diffusion wiring line.
FIG. 1 shows a block diagram of a conventional example of a semiconductor memory device. Referring to FIG. 1, the structure and operation of the semiconductor memory device will be described.
The conventional example of the semiconductor memory device such as a ROM and an EPROM is composed of an address buffer 51, a Y decoder 52, a Y selector 53, a bank decoder 54, an X decoder 55, a virtual ground (GND) selector 56, a memory cell array in a memory cell matrix 59, a precharging circuit 60, a reference memory cell section 61, a sensing circuit 62, a latch circuit 63, an output buffer 64, a control signal buffer circuit 65, an address transition detecting circuit 66, and a discharge control circuit 67. The memory cell matrix 59 is composed of a memory cell array 58 and a bank selector 57.
The address buffer 51 once holds an address signal AD supplied from an external unit such as a microprocessor, and outputs to the X decoder 55, the Y decoder 52, the bank decoder 54, the virtual ground selector 56, and the address transition detecting circuit 66. The X decoder 55 decodes the address signal AD and selects one of word line selection signals W00 to W63 to set a row of memory cells in the memory cell array 58 to a read and write enable state. The Y decoder 52 decodes the address signal AD and supplies a Y decoding signal to the Y selector 53. The Y selector 53 selects one of digit lines D0 to D4 in response to the Y decoding signal, to set one column of memory cells in the memory cell array 58 to a read enable state. Also, the Y selector 53 supplies predetermined bias voltages to ones of the digit lines D0 to D4 which are selected by the sensing circuit 62 and the precharging circuit 60.
The bank decoder 54 decodes the address signal AD and supplies one of bank selection signals BS1 to BS6 to the bank selector 57. The bank selector 57 connects or disconnects a predetermined digit line diffusion wiring line (not shown) in memory cell array 58 to or from the sensing circuit 62, the precharging circuit 60 and the virtual ground selector 56 in accordance with the bank selection signal BS1 to BS6. It should be noted that the bank selector 57 is collectively shown on the memory cell matrix 59 in FIG. 1. However, the bank selector 57 is divided into a first bank selector and a second bank selector, as mentioned later. The first bank selector selects the connection of the memory cell array 58 to the sensing circuit 62 and the precharging circuit 60, and the second bank selector selects the connection of the memory cell array 58 to the sensing circuit 62 and the virtual ground selector 56. The virtual ground selector 56 selects one of virtual ground lines VG1 to VG3 connected with the memory cell matrix 59 in accordance with the address signal AD from the address buffer 51 to supplies a ground potential GND or a power supply potential Vcc.
The memory cell matrix 59 is composed of the memory cell array 58 and the bank selector 57. The memory cell array 58 is composed of the plurality of memory cells which are arranged in a matrix, and a storage data is read out from the selected memory cell in accordance with the address signal AD. The precharging circuit 60 supplies the bias voltage to a non-selected memory cell in accordance with the position of the selected memory cell in the memory cell matrix 59. As a result, it can be prevented that the current flowing through the selected memory cell flows through the non-selected memory cell. Thus, the storage data can be surely read out. A precharge signal PC is supplied from the precharging circuit 60 to the selected digit line through a switching operation by the Y selector 53 in accordance with the address signal AD.
The reference memory cell section 61 generates a reference digit line signal DGR which is used to distinguish a read digit line signal when the storage data is read out from the selected memory cell of the memory cell matrix 59. The sensing circuit 62 compares the reference digit line signal DGR which is outputted from the reference memory cell section 61 and a digit line signal DG which is outputted from the memory cell matrix 59. Thus, the sensing circuit 62 senses the storage data which has been stored in the selected memory cell of the memory cell matrix 59 and outputs a sense output signal SO to the latch circuit 63. The control signal buffer circuit 65 generates various control signals used in the semiconductor memory device in accordance with a chip select signal CE, a read instruction signal RD, and an output enable signal OE which are supplied from the external unit such as the microprocessor. In FIG. 1, only the chip select signal CE is shown.
The address transition detecting circuit 66 detects that the address signal AD is changed, when the chip select signal CE is in a low level. At this time, the address transition detecting circuit 66 outputs address transition signals AT1 and AT2 in predetermined timings. When the chip select signal CE is in a high level, the address transition detecting circuit 66 does not output the address transition signals AT1 and AT2, even if detecting that the address signal AD is changed. It should be noted that the address transition detecting circuit 66 may generate timing signals in accordance with the transition of a clock signal instead of the address transition, when the clock signal is supplied externally.
The latch circuit 63 latches the sense output signal SO read out from the selected memory cell and detected by the sensing circuit 62, at the time of the rising edge of the address transition signal AT1 to output to the output buffer 64. The output buffer 64 outputs the sense output signal latched by the latch circuit 63 as a data output signal DOUT to the external unit such as the microprocessor. The discharge control circuit 67 discharges charge accumulated in various portions connected with the selected memory cell such as the digit line and the virtual ground (GND) line during the period of the high level of the address transition signal AT2.
Next, the detailed structure of the sensing circuit 62 will be described with reference to FIG. 2. The sensing circuit 62 is composed of a differential amplifier circuit 68, a read detecting section 69 and a reference detecting section 70. The differential amplifier circuit 68 has two input terminals, and compares output voltages from the read detecting section 69 and reference detecting section 70 to determine the storage data of the selected memory cell.
The read detecting section 69 supplies a digit line 78 with a read bias voltage. Also, the read detecting section 69 converts a read current flowing through a digit line 78 and the selected memory cell, into a read voltage to output to the differential amplifier circuit 68. The reference detecting section 70 supplies a bias voltage to a reference digit line 79. Also, the reference detecting section 70 converts a reference current flowing through the reference digit line 79 and a reference memory cell, into a reference voltage to output to the differential amplifier circuit 68.
The discharge control circuit 67 is connected with the digit lines DG and the reference digit lines DGR. Thus, the digit lines DG and the reference digit lines DGR are initialized, before the reading operation from the selected memory cell is started. The discharge control circuit 67 is composed of two N-channel MOS transistors 77. The drains of the respective transistors 77 are connected with the digit line DG 78 and the reference digit line DGR 79, respectively, and the sources thereof are both grounded. Also, the address transition signal AT2 is supplied to the gates of the transistors 77. When the address transition signal AT2 is in the high level, the transistors 77 are turned on and set the potentials of digit line DG 78 and the reference digit line DGR 79 to 0 V. When the address transition signal AT2 is in the low level, the transistors 77 are turned off to be set to the floating state.
The read detecting section 69 is composed of a P-channel MOS transistor 71, an N-channel MOS transistor 72, and two N-channel MOS transistors 73 and 74, a P-channel MOS transistor 75 and a P-channel MOS transistor 76. The P-channel MOS transistor 71 has the gate and the drain which are connected with the differential amplifier circuit 68. The N-channel MOS transistor 72 has the drain which is connected with the drain of the P-channel MOS transistor 71 and the source which is connected with the digit line DG 78. The two N-channel MOS transistors 73 and 74 have the drains which are connected with the gate of the N-channel MOS transistor 72 and the source which is connected with the ground potential GND. The P-channel MOS transistor 75 has the drain which is connected with the gate of the N-channel MOS transistor 72 and the gate which is connected with the gate of the N-channel MOS transistor 73. The P-channel MOS transistor 76 has the drain which is connected with the source of the P-channel MOS transistor 75 and the gate which is connected with the gate of the N-channel MOS transistor 74. A sense enable signal SE is supplied to the gate of the transistor 74 and 76. The transistors 72, 73 and 75 generate the predetermined read bias voltage and the transistor 72 supplies the read bias voltage from the source to the digit line DG 78. The transistor 71 functions as a load circuit of a constant current circuit, converts the read current flowing through the digit line DG 78 into a read voltage and outputs the read voltage to the differential amplifier circuit 68.
When the sense enable signal SE is in a high level, the transistor 76 is turned off and also the transistor 74 is turned on. As the result, the power supply voltage Vdd is not supplied to the drain of the transistor 75 so that the drain of the transistor 74 becomes a low level. Therefore, the transistor 72 is turned off and the supply of the read bias voltage to digit line 78 is stopped.
Oppositely, when the sense enable signal SE is in a low level, the transistor 76 is turned on and the transistor 74 is turned off. As the result, the power supply voltage Vdd is supplied to the source of the transistor 75, the transistors 72, 73 and 75 generate the read bias voltage and the supply of the read bias voltage from the source of the transistor 72 to the digit line 78 is started.
The structure of the reference detecting section 70 is the same as that of the read detecting section 69. However, the size of the load transistor 71 is different. That is, the current drive ability of the load transistor 71 is set in such a manner that the reference voltage outputted from the reference detecting section 70 is a middle voltage between the read voltage GDI(ON) and DGI(OFF), one of which is outputted to the amplifier circuit 68 in accordance with the storage data. Also, the reference detecting section 70 is different from the read detecting section 69 in the point that the source of the N-channel MOS transistor 72 is connected with not the digit line DG 78 but the reference digit line DGR 79.
Next, the detailed structure of the precharging circuit 60 is shown in FIG. 3. Referring to FIG. 3, the structure of the precharging circuit 60 is the same as the read detecting section 69 in the sensing circuit 62 shown in FIG. 2. Therefore, the description is omitted.
Next, the operation of the conventional example of the semiconductor memory device shown in FIG. 1 will be described with reference to the timing chart shown in FIGS. 4A to 4M. Referring to FIGS. 4A to 4M, it is supposed that the address signal AD is supplied from an external unit as shown in FIG. 4B, when the chip select signal CE is in the low level as shown in FIG. 4A. In this case, the address buffer 51 holds the address signal AD to supply to the internal circuits of the semiconductor memory device. Also, the address transition detecting circuit 66 generates an address transfer signal ATD (not shown) and outputs the address transition signals AT1 and AT2 as shown in FIGS. 4D and 4E). The discharge control circuit 67 stops the discharging operation of charge which has been accumulated by the digit line DG and virtual ground line VG, when the address transition signal AT2 goes to the low level as shown in FIG. 4E.
When the sense enable signal SE goes to the low level as shown in FIG. 4C, the read detecting section 69, the precharging circuit 60 and the reference detecting section 70 supply the predetermined bias voltages to the digit lines DG 78 and the reference digit line 79 respectively. The X decoder 55 decodes the address signal AD supplied from the address buffer 51, to set a selected one of the word line selection signals W00 to W63 to the high level and to set the remainder to the low level as shown in FIG. 4F. The Y decoder 52 decodes the address signal AD supplied from the address buffer 51 and outputs a digit line selection signal YSW to the Y selector 53 as shown in FIG. 4H. The Y selector 53 connects the selected digit line which is connected with the selected memory cell, with the sensing circuit 62 in response to the digit line selection signal YSW. As a result, the reading operation of the storage data from the selected memory cell becomes possible.
Also, the digit lines which are connected with the non-selected memory cells are connected with the precharging circuit 60 to make the supply of the precharge signal PC possible as shown in FIG. 4I. As a result, it can be prevented that the read bias current flows through the non-selected memory cells.
The bank decoder 54 decodes the address signal AD supplied from the address buffer 51 and outputs the bank selection signals BS1 to BS6 to the bank selector 57, as shown in FIG. 4G. The bank selector 57 connects the digit lines DG to which the read bias voltage and the precharge signal PC are supplied, with predetermined diffusion layer wiring lines in accordance with the bank selection signals BS1 to BS6. The virtual ground selector 56 decodes the address signal AD supplied from the address buffer 51 and outputs virtual ground selection signals VG1 to VG3 to the memory cell matrix 59 as shown in FIG. 4J. Here, in FIGS. 4A to 4M, the example that the virtual ground selection signal VG1 to VG3 changes to the high level is shown. Besides, the line in the low level and the line in a floating state are present.
When the word line selection signals W00 to W63, and the digit line selection signal YSW, the virtual ground selection signals VG1 to VG3 are supplied to the memory cell matrix 59, one of the memory cells is selected and the read bias voltage is supplied from the sensing circuit 62. As the result, the read current flows through the selected digit line in accordance with to the threshold of the selected memory cell as shown in FIG. 4K. The sensing circuit 62 outputs the sense output signal SO as shown in FIG. 4L, when the read data signal on the digit line DG has the sufficiently large difference, compared with the reference signal on the digit line reference DGR.
When a predetermined time elapsed after the address transfer signal ATD rises up, the address transition detecting circuit 66 sets the address transition signal AT1 to the high level as shown in FIG. 4C. The latch circuit 63 latches the sense output signal SO at the timing that the address transition signal AT1 rises up, and the output buffer 64 outputs the data output signal DOUT as shown in FIG. 4M.
When the sense enable signal SE goes to the high level as shown in FIG. 4C, the read detecting section 69, the reference detecting section 70, the precharging circuit 60 stop the supply of the predetermined bias voltage to the digit lines 78 and the reference digit line 79, respectively. The discharge control circuit 67 starts the discharging operation from the digit line DG as shown in FIG. 4K, when the address transition signal AT2 goes to the high level as shown in FIG. 4E.
By repeating the above operations, the semiconductor memory device outputs the storage data to the external unit.
There is in the conventional example of the semiconductor memory device, a problem that the read current does not flow sufficiently to the selected memory cell from which the storage data should be read out, so that a wrong storage data is read out. Also, there is another problem that the read current decreases so that the wrong storage data is read out, because many transistors intervene between the digit line terminal and the virtual ground terminal.
To solve these problems, the following technique is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 4-311900). In this reference, as shown in FIG. 1 of this reference, 2-stage bank selection circuits are arranged in the upper side and lower side of the memory cell array, respectively. Also, two digit line diffusion wiring line are connected with the drains of the respective memory cell transistors of the memory cell array from one digit line terminal, respectively. Also, in the same way, two digit line diffusion wiring lines are connected with the sources of the memory cell transistors of the memory cell array from one virtual GND terminal VG, respectively. In this way, the above-mentioned problems are tried to solve.
Certainly, there is a possibility that the problem of the erroneous reading operation of the storage data and the problem of the decrease of the reading speed can be solved in some degree. However, the problem of the erroneous reading operation of the storage data and the problem of the decrease of the reading speed are still left. Also, the bank selection circuit has a 4-stage structure so that the conventional technique can not be applied to the apparatus with the multi-stage bank selection structure. Moreover, it is necessary to connect one aluminum line to two diffusion layers in the digit line terminal or the virtual GND terminal. Therefore, the gate density of the circuit is limited by the arrangement pitch of the aluminum lines. Recently, the miniaturization of the transistor element advances and the memory cell can be made small. However, the chip area becomes large as the gate density is increased, and the wiring line connected with the memory cell become long. Therefore, because it is necessary to decrease a wiring line resistance to read the storage data at high speed, the wiring line width must be secured to some extent.
To solve the above problem, the following technique is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-96780). That is, first sub-digit lines are provided twice or {fraction (1/2+L )} times of the number of second sub-digit lines. By this, the sufficient read current can be flowed to the selected memory cell so that the storage data can be correctly read out. Also, because only the small number of transistors intervene between the digit line terminal and the virtual ground terminal, the read current is not decreased, compared with the conventional technique. Therefore, the correct data can be read out.
Here, the structure and operation of the conventional semiconductor memory device in Japanese Laid Open Patent Application (JP-A-Heisei 11-96780) will be described with reference to FIGS. 5 to 7. FIG. 5 is an equivalent circuit diagram showing the connection relation of parts in a memory cell array. FIG. 6A is a cross sectional view showing the structure of memory cell transistors T1 to T4, and FIGS. 6B to 6D are expanded equivalent circuit diagrams of the connection relation of parts in the memory cell array shown in FIG. 5.
As shown in FIG. 5 and FIGS. 6A to 6D, in the conventional virtual ground type semiconductor memory device, the plurality of memory cell transistors T1 to T4 are connected in series. The gate of each memory cell transistor is connected with one word line. FIG. 6A shows one of the plurality of word line. The source and drain of each of the memory cell transistor T1 to T4 are formed by N+ diffusion layers 93 N1 to N5. Also, the N+ diffusion layer 93 functions as the source or drain of the memory cell transistor and extends in to the column direction. The N+ diffusion layer 93 extending in the column direction is referred to as the digit line diffusion wiring line. The digit line diffusion wiring lines 88 N1, 90 N3 and 92 N5 are connected with the selected digit line 80 and function as the drains of the memory cell transistors. Also, the digit line diffusion wiring lines 89 N2 and 91 N4 are connected with the virtual ground line 85 and function as the sources of the memory cell transistors. That is, the drain N+ diffusion layer and the source N+ diffusion layer are alternately arranged in parallel. The digit line diffusion wiring lines 88, 90, 92, 89, and 91 are connected with the selected digit line 80 and the virtual ground line 85 through the bank selection transistor BT (not shown), respectively. The selected digit line 80 functions as a precharging line 81 through the switching operation of the Y selector 53. The gate of a reference memory cell transistor 86 is connected with the word line, the drain of the reference memory cell transistor 86 is connected with the reference digit line 82 and the source thereof is connected with a ground line 87.
Next, the principle in a reading operation of the storage data from the memory cell will be described in accordance with FIG. 5 and FIGS. 6A to 6D. It is now supposed that the selected memory cell 83 T2 is selected and the storage data is read out. At this time, the word line goes to the high level, and a read bias voltage of 1 V is supplied to the drain N3 of the selected memory cell transistor 83 T2 through the selected digit line 80 and the digit line diffusion wiring line 90. The source of the selected memory cell transistor T2 is grounded to 0 V through the digit line diffusion wiring line 89 and the virtual ground line 85. Therefore, as shown in FIG. 6B, the read current flows through the selected digit line 80 in accordance with the storage data (the threshold value) of the selected memory cell 83 T2.
In the same way, a bias voltage of 1 V is supplied to the drain of the reference memory cell transistor 86 through the reference digit line 82 and the reference digit line diffusion wiring line. Also, the source the reference memory cell transistor 86 is grounded to 0 V through the diffusion wiring line and the ground line 87. Therefore, the reference current flows through the reference digit line 82 in accordance with the threshold value of the reference memory cell transistor 86. The sensing circuit 62 compares the read current and the reference current to determine the storage data. In this way, the storage data can be read out.
Next, as mentioned above, the storage data of the selected memory cell 83 T2 is read out. In this case, it is supposed that the threshold value of the memory cell transistor 83 T2 is high and the read current is small (hereinafter, to be referred to as an OFF cell). Also, it is supposed that the threshold value of a neighbor non-selected memory cell transistors T3 and T4 is low and the read current is large (hereinafter, to be referred to as ON cells). When the read bias voltage is supplied to the selected digit line 80, the read bias voltage is applied to not only the drain of the selected memory cell transistor 83 T2 but also the drain of the neighbor non-selected memory cell transistor 84 T3. This state is shown in FIG. 6C. The gates of the non-selected memory cell transistors 84 T1, T3 or T4 are connected with the same word line as the selected memory cell transistor 83 is connected. Therefore, the read current flows through the non-selected memory cell transistors 84 T3 and T4, if the digit line diffusion wiring line 92 is 0 V. The sensing circuit 62 regards that the read current has flowed through the selected memory cell transistor 83 T2. As the result of this, the storage data is erroneously sensed.
In order to prevent the erroneous sensing operation, as shown in FIG. 5 and FIG. 6D, the same voltage (also, to be referred to as a precharge voltage) as the read bias voltage is applied to the digit line 81 (to be referred to as a precharging line) directly neighbor to the selected digit line 80 connected to the selected memory cell transistor 83 T2. In the example shown in FIG. 6D, the digit line diffusion wiring line 92 as the drain N5 of the transistor T4 is precharged to 1 V. Also, the potentials of the sources of the transistor T3 and T4 and the potentials of the drains thereof are set to be equal to each other. As a result, the read current does not flow through the transistor T3 and T4. In this way, even in case of FIG. 6C, the read current does not flow through the digit line diffusion wiring line 92 and it is correctly recognized that the transistor T2 is in the OFF state.
FIG. 7 shows a circuit section of the memory cell matrix of the semiconductor memory device in detail. The memory cell matrix is composed of the memory cell array 58, and the first bank selector 113, and the second bank selector 114. In this conventional example, the first and second bank selectors 113 and 114 are connected with two and four digit line diffusion wiring lines, respectively. However, the number of digit line diffusion wiring lines 105 connected with the first and second bank selectors 113 and 114 may be appropriately selected. The memory cell array 58 is composed of a plurality of memory cells 95 which are arranged in a matrix. The gate of the memory cell transistor is connected with one of the word lines 96. The word line selection signal W00 to W63 are supplied to the word lines. Also, the drain and source of the memory cell transistor 95 are connected with the digit line diffusion wiring lines 105, and are connected with the first and second bank selectors 113 and 114, respectively. That is, as to the digit line diffusion wiring lines 105, the digit line diffusion wiring line 105 connected with the first bank selector 113 and the digit line diffusion wiring line 105 connected with the second bank selector 114 are alternately arranged. Each of the memory cells is arranged between these digit line diffusion wiring lines 105. Therefore, in the memory cell transistor, the source thereof is possibly connected with the ground potential and the drain thereof is possibly connected to the sensing circuit 62.
The first bank selector 113 has two bank selection transistors BT1 and BT2 for one digit line. The drains of the bank selection transistors BT1 and BT2 are possibly connected with the digit line 80 or precharging line 81 through one of a plurality of digit line terminals 97 to 101 and the Y selector 53. Also, the gates of the bank selection transistors BT1 and BT2 are connected with the bank selection lines 106 and 107, respectively. Also, the bank selection signals BS1 and BS2 are supplied to the bank selection lines 106 and 107. Also, the sources of the bank selection transistors BT1 and BT2 are connected with the digit line diffusion wiring lines 105 in the memory cell array 58.
A precharge signal PC is supplied to the digit line diffusion wiring line 105 which is selected in accordance with the bank selection signal BS1 and BS2 by the first bank selector 113, when the read bias voltage is supplied to one of the digit line terminals 97 to 101. The second bank selector 114 has four bank selection transistors 112 BT3 to BT6 for one virtual ground line. The source of each of the bank selection transistors 112 BT3 to BT6 is connected with a corresponding one of a plurality of virtual ground terminals 102 to 104, and is connected with the ground potential through the virtual ground selector 56. Also, the gate of each of the bank selection transistors 112 BT3 to BT6 is connected with a corresponding one of the bank selection lines 108 to 111. The bank selection signals BS3 to BS6 are supplied to the bank selection lines 108 to 111, respectively. The drain of each of the bank selection transistors 112 BT3 to BT6 is connected with the digit line diffusion wiring line 105 on the source side of the memory cell transistor. The digit line diffusion wiring line 105 is selected in accordance with the bank selection signals BS3 to BS6 by the second bank selector 114. The selected digit line diffusion wiring line 105 is connected with the source of the selected memory cell 83 (FIG. 5 and FIGS. 6A to 6D) to allow the read current to flow through the selected memory cell 83.
Next, the memory cell matrix 59 shown in FIG. 7 will be described with reference to a truth table shown in FIG. 8. Referring to FIG. 8, columns a2, a1, a0 show lower 3 bits of the accessed address signal AD, and a column AD is the hexadecimal representation. Also, a column CEL shows a number n of the selected memory cells SXn (n=1 to 8 in FIG. 7). Columns D0 to D4, columns VG1 to VG3, columns BS6 to BS1 show the signal levels of the digit line terminals, the signal levels of the virtual ground terminals, and the signal levels of the bank selection lines, respectively.
The case will be described in which lower 3 bits [a2, a1, a0] of the accessed address signal AD are [1, 1, 1], and the storage data is read out from the memory cell SX1 (FIG. 7). The memory cell SX1 is connected with the word line selection signal W63 in the hexadecimal representation on the word lines 96. At this time, the word line selection signal W63 is in the high level and the other word line selection signals W00 to W62 are in the low level. The bank selection signals BS6 and BS2 are in the high level in accordance with the address signal AD, and the other bank selection signals are in the low level. Therefore, the transistor BT2 in the first bank selector 113 is turned on and the transistor BT1 is turned off. Also, the transistor BT6 in the second bank selector 114 is turned on and the bank selection transistors BT3 to BT5 are turned off. The digit lines connected with the digit line terminals D2 and D3 are in the high level and the digit lines connected with the digit line terminals D0, D2 and D4 are in the floating state. Also, the virtual ground selection signal VG2 which is supplied to the virtual GND terminals 102 to 104 is in the low level, the virtual ground terminal VG3 is in the high level and the virtual ground terminal VG1 is in the floating state.
The read bias voltage is supplied from the sensing circuit 62 to the drain of the selected memory cell SX1 through the Y selector 53, the digit line terminal 99 D2, the transistor BT2 and the digit line diffusion wiring line 105. On the other hand, the virtual ground terminal 103 VG2 in the low level is connected to the source of the transistor SX1 through the transistor BT6 and the digit line diffusion wiring line 105. Therefore, the drain of the memory cell transistor SX1 is about 1 V, the source thereof becomes 0 V. As a result, the read current flows from the digit line terminal 99 D2 to the virtual ground terminal 103 VG2 in accordance with the storage data of the memory cell SX1.
Here, it is supposed that the threshold of the memory cells SX2 to SX8 are low (ON cells) so that the read current flows. In this case, the read bias voltage supplied to the selected memory cell charges the digit line diffusion wiring lines 105 connected with the memory cells SX2 to SX8. Therefore, the read current flows through the memory cells SX2 to SX8 even if the threshold of the memory cell SX1 is high (OFF cell) so that the read current does not flow. As a result, the sensing circuit 62 erroneously senses the storage data of the memory cell SX1.
To prevent this problem, the same voltage as the read bias voltage is applied to the virtual ground terminal 104 VG3 and the digit line terminal 100 D3 to prevent pseudo-read current from flowing. This voltage is referred to as a precharge voltage. The precharge voltage PC is supplied from the digit line terminal 100 D3 to the non-selected memory cells SX5 to SX2 through the transistor BT2 and the digit line diffusion wiring line 115. In the same way, the precharge voltage PC is supplied from the virtual ground terminal 104 VG3 to the non-selected memory cells SX8 to SX2 through the transistor BT6 and the digit line diffusion wiring line 105. At this time, the potentials of the drain of the non-selected memory cell transistors SX8 to SX2 become equal to the source potentials thereof. Therefore, the pseudo-read current never flows.
Next, as shown in FIG. 7, it is supposed that the bank selection signals BS5 and BS2 are in the high level and the other bank selection signals are in the low level in accordance with the address signal AD. Therefore, the transistor BT2 in the first bank selector 113 is turned on, the transistor BT1 is turned off, the transistor BT5 in the second bank selector 114 is turned on and the transistors BT3, BT4 and BT6 are turned off. Also, the signals on the digit lines connected with the digit line terminals D1 and D2 are in the high level and the signals on the digit lines connected with the digit line terminals D0, D3 and D4 are in the floating state. Also, the virtual ground terminal 103 VG2 is in the low level, the virtual ground terminal 102 VG1 is in the high level and the virtual ground terminal VG3 is in the floating state. Therefore, the read current flows in order of the digit line terminal 99 D2xe2x86x92the transistor BT2xe2x86x92the digit line diffusion wiring line 105xe2x86x92the selected memory cell SX2xe2x86x92the digit line diffusion wiring line 105xe2x86x92the transistor BT5xe2x86x92the virtual ground terminal 103 VG2.
When the memory cell SX2 is selected, the precharge voltage is applied to the virtual ground terminal 102 VG1 and the digit line terminal 98 D1 to prevent the pseudo-read current from flowing on the side of the non-selected memory cell SX1. In this way, the portion supplied with the precharge voltage is dependent on the location of the selected memory cell in the memory cell array 58. In other words, the precharge voltage is applied to the digit line terminal neighbor to the selected digit line terminal on the side of the source of the selected memory cell. Also, the precharge voltage is applied to the virtual ground terminal neighbor to the selected virtual ground terminal on the side of the source of the selected memory cell. The reading operation is carried out in accordance to the truth table shown in FIG. 8 as for the other memory cells SX3 to SX8.
Hereinafter, the device structure of the memory cell matrix 59 and the peripheral portion will be described with reference to FIG. 9 to FIG. 11. FIG. 9 shows a plan view of a portion of the memory cell matrix 59. FIG. 10 shows a cross sectional view along the line Axe2x80x94A of FIG. 9, and FIG. 11 shows a cross sectional view along the line Bxe2x80x94B of FIG. 9.
Referring to FIG. 9, the memory cell matrix 59 is composed of the memory cell array 58, and the first and second bank selectors 113 and 114. Generally, the memory cell matrix 59 is composed of a plurality of memory cell arrays, and the plurality of bank selectors. Also, the virtual ground lines 85 (VG1, VG2, and so on) and the digit lines 78 (D0, D1, D2, and so on) are arranged to connect these memory cell arrays and the bank selectors. Also, the digit lines 78 and the virtual ground lines 85 are formed of metal such as aluminum and copper or silicide such as WSi to reduce the wiring line resistance.
The digit lines 78 (D0, D1, D2, and so on) are respectively connected with the digit line terminals (97, 98, 99, and so on) which are composed of N+ diffusion layers through the plugs (120, 122 and so on). The virtual ground lines 85 (VG1, VG2, and so on) are respectively connected with the virtual ground terminals (102, 103, and so on) which are composed of N+ diffusion layers through the plug (123, 124 and so on). The N+ diffusion layers connected with the digit line terminals (97, 98, 99, and so on) function as the drains of the bank selection transistors BT1 and BT2. The N+ diffusion layers connected with the virtual ground terminals (102, 103, and so on) function as the sources of the bank selection transistors BT3 to BT6.
Also, the digit line diffusion wiring lines 105 which are composed of N+ diffusion layers are formed in parallel to the above mentioned N+ diffusion layers. The N+ diffusion layers function as the sources of the bank selection transistors BT1 and BT2 and function as the drains of the bank selection transistors BT3 to BT6. Also, in the memory cell array 58, the N+ diffusion layers connected with the bank selection transistors BT1 and BT2 function as the drains of the memory cell transistors. The N+ diffusion layers connected with the bank selection transistors BT3 to BT6 function as the sources of the memory cells. The bank selection transistors 112 (BT1 to BT6) are formed between the digit line diffusion wiring line 105 and one of the digit line terminals or one of the virtual ground terminals under the bank selection lines. The memory cell transistor is formed between the N+ diffusion layers of the two digit line diffusion wiring lines 105 under the word lines 96. Also, in FIG. 9, the rectangular region shown by slanted lines is a channel stopper region where P+ impurities are injected.
Referring to FIG. 10, the N+ diffusion layers 93 are embedded in a predetermined interval. The N+ diffusion layer 93 functions as the source or drain of the memory cell transistor and bank selection transistor and as the digit line diffusion wiring lines. An ion implanted channel 126 of the ON cell or an ion non-implanted channel 127 of the OFF cell is formed in the channel region between the N+ diffusion layers 93 in accordance with the storage data. A gate insulating film 94 is formed on the P-channel substrate 125 and the N+ diffusion layer 93, and the word lines 96 are formed on the gate insulating film 94. A lower interlayer insulating film 128 is formed on the word lines 96 and a metal wiring lines D0, VG1, D1, D2, VG2 are arranged in a predetermined interval on the interlayer insulating film 128. Moreover, an upper interlayer film 128 is formed on the metal wiring lines 129 and the interlayer film 128.
Referring to FIG. 11, the N+ diffusion layers 93 are embedded in consideration of the arrangement of the word lines 96. A plug is arranged on one of the N+ diffusion layers 93. The gate insulating films 94 are arranged in a predetermined interval on the N+ diffusion layers and the P-channel substrate 125. The word lines 96 are arranged on the gate insulating films 94. Moreover, the lower interlayer insulating films 128 exist on the N+ diffusion layers 93, the P-channel substrate 125 and the word lines 96. Metal wiring lines 129 are arranged on the lower interlayer insulating film 128 and the plugs, and the upper interlayer insulating film 128 is again arranged on the metal wiring lines 129. In this way, the digit line 78 D0 is connected with the digit line terminal 97 as the N+ diffusion layer 93 through the plug 120, and functions as the drain of the bank selection transistor 112. Also, the N+ diffusion layer 93 direct below the word lines 96 functions as the source of the memory cell transistor.
In this way, because the virtual ground type memory cell array 58 can be formed without providing a plug for every memory cell, a lot of memory cells can be formed in the minimum area. Also, because the digit lines function as main digit lines and the digit line diffusion wiring lines function as sub-digit lines, a parasitic capacity and a leak current of the memory cell can be reduced when being seen from the sensing circuit.
Referring to FIG. 9 again, in the semiconductor memory device of this conventional example, the plurality of digit lines 78 and the plurality of virtual ground lines 85 extend in parallel over a long distance. Also, the digit lines 78 and the virtual ground lines 85 are different from each other in the number, and the kind of the wiring line which is present in neighbor to each wiring line depends on the position of the memory cell. Moreover, as shown in FIG. 8, because the levels of the signals supplied to each digit line 78 and each virtual ground line 85 are different, dependent on the address signal AD, the influence situation of coupling noise depends on the state of the neighbor signal.
As shown in FIGS. 12A to 12D and FIGS. 13A to 13D, the phenomenon that the charging operation speed of the digit line depends on the state of the neighbor digit line will be described.
FIGS. 12A to 12D show a rising characteristic of the digit line 78 when the voltage value of a digit line or virtual ground line neighbor to the selected digit line 78 (hereinafter, to be referred to as a neighbor line) does not change. FIGS. 13A to 13D show a rising characteristic of the digit line 78 when the voltage value of the neighbor line to the selected digit line 78 changes. FIG. 12A and FIG. 13A show the time changes of the read bias voltage V1 supplied to the selected digit line 80 from the sensing circuit 62. FIG. 12B and FIG. 13B show the time changes of the precharge signals V2 supplied to the neighbor line from the precharging circuit 60. FIG. 12C and FIG. 13C show the time changes of the coupling noise voltages VN which the precharge signal V2 supplied to the neighbor line gives to the selected digit lines 78. FIG. 12D and FIG. 13D show the time changes of output voltages V0 to the sensing circuit 62.
When the read bias voltage V1 is applied to the selected digit line 78 as shown in FIG. 12A, the read current flows through the selected digit line 78 and the selected memory cell. By this, as shown in FIG. 12D, the output voltage V0 is outputted to the sensing circuit 62. This output voltage V0 is gradually increased after a delay time lapses. In the example shown in FIGS. 13A to 13D, the read bias voltage V1 is applied to the selected digit line 78, and the output voltage V0 is outputted to the sensing circuit 62, as in the example shown in FIGS. 12A to 12D. However, as shown in FIG. 13C, the selected digit line 78 receives the influence of the coupling noise voltage VN from the neighbor line in accompaniment with the increase of the precharge voltage V2. Therefore, the output voltage V0 in which the coupling noise voltage VN is superimposed on the output voltage V0 shown in FIG. 12D is outputted to the sensing circuit 62.
In this way, when the precharge signal is supplied to the neighbor line at the same time as the read bias voltage, the output voltage outputted to the sensing circuit becomes as if the rising time or the delay time becomes short, compared with the example shown in FIG. 12D.
FIGS. 14A and 14B show the time changes of the output voltages DG1 and DG2 on the digit lines 78 and the reference voltage DGR on the reference digit line 79. The output voltage DG1 or DG2 and the reference voltage DGR are supplied to the sensing circuit 62. Here, the output voltages DG1(ON) and DG2(ON) show the voltages generated from the ON cells, and the output voltages DG1(OFF) and DG2(OFF) show the voltages generated from the OFF cell. Also, FIG. 14A shows a case that the influences of the coupling noise to the digit line 78 is small, and FIG. 14B shows a case that the influences of the coupling noise to the digit line 78 is large.
As shown in FIG. 14A, the influences of the coupling noise to the digit lines 78 and the reference digit line 79 are small. Therefore, the output voltages DG1(ON) and DG1(OFF) and the reference voltage DGR have substantially the same rising characteristic. In FIG. 14A, a period is long from time when that reading operation is made possible to time when the difference between the output voltage DG1(ON) or DG1(OFF) and the reference voltage DGR becomes large so that the sensing circuit 60 can sense the storage data from the selected memory cell.
On the other hand, as shown in FIG. 14B, when the digit line 78 undergoes the influence of the coupling noise from the neighbor line, the rising operation of the output voltage DG2(ON) or DG2(OFF) becomes faster than the rising operation of the reference voltage DGR. However, because the output voltage is sensed at the same time t2 as in the case shown in FIG. 14A, the sensing circuit 62 erroneously senses both of the ON cell and the OFF cell to be the OFF cell. Also, to correctly sense the output voltages DG2(ON) and DG2(OFF), it is necessary to wait until the time t3. Therefore, the read time becomes long so that the efficiency of the semiconductor memory device is degraded.
In this way, in Japanese Laid Open Patent Application (JP-A-Heisei 4-311900), because a digit line and a virtual ground line are alternately arranged, the coupling noise is the same, so that the above mentioned problem can be avoid, even if which of memory cells is selected. However, the above mentioned problem is caused, when the arrangement of the memory cell matrix shown in Japanese Laid Open Patent Application (JP-A-Heisei 11-96780) is adopted to improve an integration density.
In recent years, the operation speed of a microprocessor is increased remarkably, and still more improvement is demanded about the operation speed of a semiconductor memory device connected with the microprocessor. As described above, the charging operation speed of the selected digit line is different for every address. On the other hand, the charging operation speed of the reference digit line is constant. Therefore, if the charging operation speed of the reference digit line is designed in accordance with the digit line with a slow charging operation speed, it is difficult to accomplish the high speed reading operation of the storage data from the memory cell. Oppositely, if the charging operation speed of the reference digit line is designed in accordance with the digit line with the fastest charging operation speed and the sensing operation is carried out in a short time, the sensing circuit erroneously senses the output voltage on the digit line.
Therefore, an object of the present invention is to provide semiconductor memory device in which the integration density can be increased and a plurality of digit lines are provided between virtual ground lines.
Another object of the present invention is to provide a semiconductor memory device with no address dependency in a reading operation speed of a storage data from a memory cell.
Still another object of the present invention is to provide a semiconductor memory device in which a reading operation can be carried out in accordance with a digit line with the fastest reading speed without depending on the structure of the digit lines.
Yet still another purpose of the present invention is to provide a semiconductor memory device which a high speed reading operation of a memory cell storage data is possible regardless of the structure of a memory cell matrix.
In order to achieve an aspect of the present invention, a semiconductor memory device includes a memory cell matrix section, a reference memory cell matrix section and a sensing circuit. The memory cell matrix section includes memory cells arranged in a first matrix. When one of the memory cells is selected based on an address signal, a read data signal corresponding to a storage data of the selected memory cell is outputted. The reference memory cell matrix section includes reference memory cells arranged in a second matrix, and outputs a reference data signal for the read data signal from the selected memory cell. The sensing circuit senses the storage data based on the read data signal from the memory cell matrix section and the reference data signal from the reference memory cell matrix section. At this time, the reference memory cell matrix section outputs the reference data signal to the sensing circuit such that the reference data signal appears in substantially synchronous with the data read signal.
Here, the reference memory cell matrix section may output the reference data signal to the sensing circuit based on the address signal.
Also, each of the memory cells may be connected to either one of word lines and each of the reference memory cells may be connected to either one of the word lines.
Also, the reference memory cell matrix section may include a reference memory cell matrix, a first selector, a first bank selector, a second selector and a second bank selector. The reference memory cell matrix includes the reference memory cells arranged in the second matrix. A selected one of the reference memory cells is connected to a first digit line, and remaining ones of the reference memory cells are non-selected reference memory cells. The first selector applies a read bias for the selected reference memory cell. Also, the first selector applies a first reference precharge signal for a second reference digit line connected with a first one of the non-selected reference memory cells to provide a correct current path for the reference data signal. The first bank selector transfers the read bias to the first digit line and the first reference precharge signal to the second digit line. The second selector applies a ground voltage and a second reference precharge signal for the reference memory cell matrix. The second bank selector transfers the ground voltage to a third digit line connected with the selected reference memory cell and the second reference precharge signal to a fourth digit line connected with a second one of the non-selected memory cells. At this time, the reference data signal corresponds to a current flowing through the first digit line, the selected reference memory cell and the third digit line, when the read bias is applied to the selected reference memory cell. In this case, the memory cells may be arranged to form the first matrix of basic repetition units. Also, the reference memory cell matrix section may include the reference memory cells which are arranged to have the same structure as a basic repetition unit of the memory cells in the memory cell matrix section.
Also, the reference memory cell matrix section may include a reference memory cell matrix, a first selector, a first bank selector, a second selector and a second bank selector. The reference memory cell matrix includes the reference memory cells arranged in the second matrix. A selected one of the reference memory cells is connected to a first digit line, and remaining ones of the reference memory cells are non-selected reference memory cells. The first selector applies a read bias for the selected reference memory cell. Also, the first selector applies a first reference precharge signal for a second reference digit line connected with a first one of the non-selected reference memory cells based on the address signal to provide a correct current path for the reference data signal. The first bank selector transfers the read bias to the first digit line and the first reference precharge signal to the second digit line based on the address signal. The second selector applies a ground voltage and a second reference precharge signal for the reference memory cell matrix based on the address signal. The second bank selector transfers the ground voltage to a third digit line connected with the selected reference memory cell and the second reference precharge signal to a fourth digit line connected with one of the non-selected memory cells based on the address signal. At this time, the reference data signal corresponds to a current flowing through the first digit line, the selected reference memory cell and the third digit line, when the read bias is applied to the selected reference memory cell. In this case, the memory cells may be arranged to form the first matrix of basic repetition units. Also, the reference memory cell matrix section may include the reference memory cells which are arranged to have the same structure as a basic repetition unit of the memory cells in the memory cell matrix section. Also, the first and second bank selection signals may be generated based on the address signal to select the selected memory cell in the memory cell matrix section.
Also, the reference memory cell matrix section may include a reference memory cell matrix, a third selector, a first bank selector, a second selector and a second bank selector. The reference memory cell matrix includes the reference memory cells arranged in the second matrix. A reference digit wiring line and a reference virtual ground wiring line are alternately provided to extend in a column direction and the reference memory cells of each row are provided between the reference digit wiring line and the reference virtual ground wiring line in a row direction. One of the reference memory cells selected based on the address signal is connected to a first one of the reference digit wiring lines, and remaining ones of the reference memory cells are non-selected reference memory cells. The third selector applies a read bias for the first reference digit wiring line connected to the selected reference memory cell. Also, the third selector applies a first reference precharge signal for a second one of the reference digit wiring lines connected with a first one of the non-selected reference memory cells based on one of bias patterns which is determined based on the address signal. The bias patterns is predetermined based on a first number and a second number. The first bank selector includes first bank selection transistors which are grouped in units of the first numbers. Also, the first bank selector transfers the read bias to the first digit wiring line and the first reference precharge signal to the second digit wiring line based on the address signal using the first bank selection transistors. The second selector applies a ground voltage and a second reference precharge signal for the reference memory cell matrix based on the one bias pattern. The second bank selector includes second bank selection transistors which are grouped in units of the second numbers. Also, the second bank selector transfers the ground voltage to a first one of the virtual ground wiring lines connected with the selected reference memory cell and the second reference precharge signal to a second one of the virtual ground wiring lines connected with one of the non-selected memory cells based on the address signal using the second bank selection transistors. At this time, the reference data signal corresponds to a current flowing through the first digit wiring line, the selected reference memory cell and the first virtual ground wiring line, when the read bias is applied to the selected reference memory cell. In this case, two of the reference memory cells connected one of the reference digit wiring line has a same storage data.
Also, the reference memory cell matrix section may include a plurality of reference digit lines which have different resistance and different parasitic capacities, respectively, a plurality of virtual ground lines connected to a ground potential, a reference memory cell matrix, a fifth selector, a first bank selector, and a second bank selector. The reference memory cell matrix includes the reference memory cells arranged in the second matrix. A reference digit wiring line and a reference virtual ground wiring line are alternately provided to extend in a column direction and the reference memory cells of each row are provided between the reference digit wiring line and the reference virtual ground wiring line in a row direction. One of the reference memory cells selected based on the address signal is connected to a first one of the reference digit wiring lines, and remaining ones of the reference memory cells are non-selected reference memory cells. The fifth selector selects a first one of the plurality of reference digit lines and a second one of the plurality of reference digit line. Also, the fifth selector applies a read bias for the first reference digit line to be connected to the selected reference memory cell. Also, the fifth selector applies a first reference precharge signal for the second reference digit line connected with a first one of the non-selected reference memory cells based on one of bias patterns which is determined based on the address signal, the bias patterns being predetermined based on a first number and a second number. The first bank selector includes first bank selection transistors which are grouped in units of the first numbers. The first bank selector transfers the read bias from the first reference digit line to the first digit wiring line and the first reference precharge signal from the second digit line to a second one of the digit wiring lines based on the address signal using the first bank selection transistors. The second bank selector includes second bank selection transistors which are grouped in units of the second numbers. Also, the second bank selector connects the ground voltage to a first one of the plurality of virtual ground wiring lines connected with the selected reference memory cell and a second reference precharge signal to a second one of the plurality of virtual ground wiring lines connected with one of the non-selected memory cells based on the address signal using the second bank selection transistors. At this time, the reference data signal corresponds to a current flowing through the first reference digit line, the first digit wiring line, the selected reference memory cell and the first virtual ground wiring line, when the read bias is applied to the selected reference memory cell. In this case, two of the reference memory cells connected one of the reference digit wiring line has different storage data.
Also, the reference memory cell matrix section may include a plurality of reference digit lines, a virtual ground line, a reference memory cell matrix, a selective precharging circuit, a first bank selector, and a second bank selector. The reference memory cell matrix includes the reference memory cells arranged in the second matrix. A reference digit wiring line and a reference virtual ground wiring line are alternately provided to extend in a column direction and the reference memory cells of each row are provided between the reference digit wiring line and the reference virtual ground wiring line in a row direction. One of the reference memory cells selected based on the address signal is connected to a first one of the reference digit wiring lines, and remaining ones of the reference memory cells are non-selected reference memory cells. The selective charging circuit applies a read bias for a first of the plurality of reference digit lines which is connected to the selected reference memory cell. Also, the selective charging circuit applies a reference precharge signal for a second one of the plurality of reference digit lines which is connected with a first one of the non-selected reference memory cells. A value of the reference precharge signal is determined based on the address signal. The first bank selector transfers the read bias from the first reference digit line to the first reference digit wiring line and the reference precharge signal from the second reference digit line to the second reference digit wiring line based on a first bank selection signal. The second bank selector connects the ground voltage to the virtual ground wiring line connected with the selected reference memory cell based on a second bank selection signal, the first and second bank selection signals being determined based on the address signal. At this time, the reference data signal corresponds to a current flowing through the first reference digit line, the first reference digit wiring line, the selected reference memory cell and the virtual ground line, when the read bias is applied to the selected reference memory cell. In this case, two of the reference memory cells connected one of the reference digit wiring line may have different storage data. Also, the selective charging circuit may apply the reference precharge signal for the second reference digit line in response to the first and second bank selection signals. Also, the selective charging circuit may include a plurality of transistors supplying a plurality of currents as the reference precharge signal based on the address signal. In this case, the plurality of transistors may have different current supply capabilities, and each of the plurality of transistors are selectively turned on based on the address signal. Also, the plurality of transistors may have different gate widths. Alternatively, the plurality of transistors may have different gate lengths.
Also, each of the memory cell matrix section and the reference memory cell matrix section includes a bank selector section. At this time, the semiconductor memory device may further includes a bank decoder decoding the address signal.
Also, the semiconductor memory device may further include an X decoder decoding the address signal to specify one of word lines which are common to the memory cell matrix section and the reference memory cell matrix section.
Also, a semiconductor memory device includes a memory cell matrix section, a reference memory cell matrix section and a sensing circuit. The memory cell matrix section includes memory cells are arranged in a first matrix. When one of the memory cells is selected based on an address signal, the selected memory cell is connected to a first column wiring line. Also, a precharge signal is applied to at least one second column wiring line connected to one of the memory cells other than the selected memory cell and a read data signal corresponding to a storage data of the selected memory cell is outputted. The reference memory cell matrix section includes reference memory cells arranged in a second matrix. The reference memory cell matrix section outputs a reference data signal for the read data signal from the selected memory cell, the reference data signal corresponding to influence of the precharge signal to the read data signal. The sensing circuit senses the storage data based on the read data signal from the memory cell matrix section and the reference data signal from the reference memory cell matrix section. At this time, the reference memory cell matrix section outputs the reference data signal to the sensing circuit such that the reference data signal appears in substantially synchronous with the data read signal.
Also, a semiconductor memory device includes a memory cell matrix section, a reference memory cell matrix section and a sensing circuit. The memory cell matrix section includes memory cells are arranged in a first matrix. When one of the memory cells is selected based on an address signal, the selected memory cell is connected to a first column wiring line. At this time, a precharge signal is applied to at least one second column wiring line connected to one of the memory cells other than the selected memory cell and a read data signal corresponding to a storage data of the selected memory cell is outputted. The reference memory cell matrix section includes reference memory cells arranged in a second matrix. The reference memory cell matrix section outputs a reference data signal from a selected one of the reference memory cells corresponding to the selected memory cell, wherein the selected reference memory cell is connected a reference digit line whose charging speed is controlled based on influence of the precharge signal to the read data signal. The sensing circuit senses the storage data based on the read data signal from the memory cell matrix section and the reference data signal from the reference memory cell matrix section. At this time, the reference memory cell matrix section outputs the reference data signal to the sensing circuit such that the reference data signal appears in substantially synchronous with the data read signal.